The present invention relates to a semiconductor device and a method for manufacturing the same and more particularly to a semiconductor device having a high voltage p-channel transistor and a method for manufacturing the same.
A high voltage p-channel MIS (Metal Insulator Semiconductor) transistor is a transistor in which the region between a gate electrode and a drain electrode is larger than an ordinary p-channel MIS transistor and the p-type impurity concentration of the region is low. In this type of transistor, the electric field between the gate electrode and drain electrode is mitigated, so the withstand voltage is high. For example, a p-channel MIS transistor which uses a wider p-type well region than usual as an impurity region to obtain a drain electrode is disclosed in “Effect of mechanical stress on LDMOSFETs: Dependence on orientation and gate bias,” authored by Aghoram U, Liu J, Chu M, Koehler A D, Thompson S E, Sridhar S, Wise R, Pendharkar S, Denison M (USA, IEEE, ISPSD '09, 2009, pp. 220-223). In this case, the p-type well region coupled to the drain electrode stretches to the gate electrode from the drain electrode in away to overlap the gate electrode in a plan view.